Zhishuai Zhang received his B.E. and Ph.D. degrees from Tsinghua University. His research focuses on analog/mixed-signal integrated circuit design—especially SAR ADCs and emerging amplifiers—as well as LLM-driven automation for mixed-signal IC design and agentic engineering for chip design.
He has held long-term visiting appointments at the University of Hong Kong and ETH Zürich, and has visited leading universities including the National University of Singapore, Waseda University, and the University of Tokyo. He has received international honors including the IEEE Solid-State Circuits Society Student Circuit Contest Award, the ISSCC Jack Kilby Outstanding Student Paper Award, and the ISSCC Student Travel Grant Award, as well as domestic funding and honors including support from the National Natural Science Foundation of China, the China Education Development Foundation Endeavor Scholarship, the MIIT–MOE Special Scholarship for High-Level IC Talent Development (Tier A), the Zhihua Integrated Circuit Scholarship, the Feng Chongxi Scholarship, and the Special Prize of the “Liu Runsheng Outstanding Teaching Assistant Award” from the Department of Electronic Engineering at Tsinghua University.
SAR ADCs, pipelined-SAR ADCs, emerging amplifiers, and related topics; architectural reconfiguration and multi-mode concurrency for programmable A/D converter arrays.
Large-language-model–driven automation for mixed-signal IC design: from hierarchical compilation methods to structured reasoning for I/O schematic and layout generation.
Connecting LLM agents to Cadence Virtuoso through open infrastructure such as Virtuoso-Bridge, turning repetitive manual work into automated workflows.
Also visited for short-term academic exchange:
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Infrastructure for agentic analog & mixed-signal design
Drive Cadence Virtuoso locally or remotely with workflows for SKILL execution, layout, schematic, Maestro, and Spectre—so LLM agents can call the design platform and turn repetitive manual work into automation.
Toolbox for ADC modeling, spectrum analysis, and calibration
An open-source toolbox for data-converter analysis and verification.
Agent skill for gm/Id characterization and gm/Id-based design
Agent skill for simulating gm/Id characteristics and supporting gm/Id-based analog design.
Curated agent skills for analog and mixed-signal IC design
A collection of agent skills for analog and mixed-signal (AMS) IC design.
Agent skills for Verilog-A
Agent skills for working with Verilog-A.
Event-driven Verilog-A simulator
Event-driven Verilog-A Simulator. Zero-dependency and fast to respond—ideal for verifying clock, control, and calibration logic.
