张智帅博士Zhishuai ZhangPhD

张智帅本科与博士均毕业于清华大学。长期从事 SAR ADC、新型放大器等数模混合信号集成电路设计研究，致力于大语言模型驱动的混合信号集成电路设计自动化，并热衷于面向芯片设计的智能体工程技术。

曾在香港大学、瑞士苏黎世联邦理工学院进行长期访问，并赴新加坡国立大学、日本早稻田大学、东京大学等知名高校开展交流。曾获 IEEE Solid-State Circuits Society 学生电路设计竞赛奖、ISSCC Jack Kilby Outstanding Student Paper Award、ISSCC Student Travel Grant Award 等国际奖项，以及国家自然科学基金、中国教育发展基金会奋进奖学金、教育部·工信部集成电路高层次人才培养专项奖学金（A 档）、志华集成电路奖学金、冯重熙奖学金、清华大学电子工程系“刘润生优秀助教奖”特等奖等国内资助与荣誉。

研究方向

数模混合信号集成电路设计

SAR ADC、Pipe-SAR ADC、新型放大器等；可编程 A/D 转换器阵列的架构重构与多模式并发。

LLM 驱动的设计自动化

大语言模型驱动的混合信号集成电路设计自动化：从层次化编译方法到 I/O 原理图与版图生成的结构化推理。

面向芯片设计的智能体工程

以 Virtuoso-Bridge 等开源基础设施连接 LLM Agent 与 Cadence Virtuoso，把重复性手工作业转化为自动化工作流。

教育背景

  1. 2016 – 2021

    清华大学

    本科 · 学士

    导师孙楠 (Nan Sun)

    2018.06 – 2018.08

    香港大学

    访问研究

    导师Ngai Wong

  2. 2021 – 2026

    清华大学

    直博 · 工学博士

    导师孙楠 (Nan Sun)

    2025.08 – 2026.01

    苏黎世联邦理工学院（ETH Zürich）

    访问研究

    导师Taekwang Jang

另曾赴以下高校开展短期学术交流：

学术论文

  1. A 0.0035mm² 86dB-SNR 1.25MHz-BW Noise-Shaping SAR ADC Enabling kT/C Noise Shaping
    Xing Wang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie
    IEEE Journal of Solid-State Circuits (JSSC)2026
    DOIIEEE谷歌学术Semantic Scholar
  2. A 13b 500MS/s 94dB-SFDR Resistive-Input Pipelined-SAR ADC with Linear and Efficient Current-Buffer-Based Integrating Sampler
    Xiyu He, Mingyang Gu, Yunsong Tao, Siyu Huang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie
    IEEE International Solid-State Circuits Conference (ISSCC)2026
    DOIIEEE谷歌学术Semantic Scholar
  3. AMS-IO-Bench and AMS-IO-Agent: Benchmarking and Structured Reasoning for Analog and Mixed-Signal Integrated Circuit Input/Output Design
    Zhishuai Zhang*, Xintian Li*, Shilong Liu, Aodong Zhang, Lu Jie, Nan Sun
    AAAI Conference on Artificial Intelligence (AAAI)2026
    DOIAAAI谷歌学术Semantic Scholar
  4. Live Demonstration: LLM-Based Agent for Interactive Multi-Process I/O Schematic and Layout Generation
    Zhishuai Zhang*, Zengchun Chen*, Xintian Li*, Shilong Liu, Aodong Zhang, Lu Jie, Nan Sun
    IEEE International Symposium on Circuits and Systems (ISCAS)2026
    DOIIEEE谷歌学术Semantic Scholar
  5. SpecMind: Automated and Interpretable Multi-Agent Diagnosis of Analog-to-Digital Converter (ADC) Failures
    Zhishuai Zhang*, Kezhuo Liu*, Aodong Zhang, Shilong Liu, Nan Sun, Lu Jie
    International Symposium of EDA (ISEDA)2026
    谷歌学术Semantic Scholar
  6. A 0.0035mm² 86dB-SNR 1.25MHz-BW Noise-Shaping SAR ADC Enabling kT/C Noise Shaping
    Xing Wang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie
    IEEE Symposium on VLSI Technology and Circuits2025
    DOIIEEE谷歌学术Semantic Scholar
  7. A 0.16mm² 450MHz-BW 72dB-SNDR Continuous-Time Pipeline ADC with APF+HPF and APF+FIR Hybrid Delay Alignment Techniques
    Heyang Zhao*, Yuxuan He*, Yunsong Tao, Zhishuai Zhang, Yi Zhong, Lu Jie, Nan Sun
    IEEE Custom Integrated Circuits Conference (CICC)2025
    DOIIEEE谷歌学术Semantic Scholar
  8. A 70dB-SNDR 80MHz-BW Filter-Embedded Pipe-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating Charge-Transfer Amplifier
    Siyu Huang, Zhishuai Zhang, Xiyu He, Mingyang Gu, Yunsong Tao, Yi Zhong, Nan Sun, Lu Jie
    IEEE International Solid-State Circuits Conference (ISSCC)2025
    DOIIEEE谷歌学术Semantic Scholar
  9. A Filter-Embedded Pipe-SAR ADC with Progressive Conversion and Floating Charge Transfer Amplifier
    Siyu Huang, Zhishuai Zhang, Xiyu He, Lu Jie
    IEEE Journal of Solid-State Circuits, vol. 60, no. 12, pp. 4503–45142025
    DOIIEEE谷歌学术Semantic Scholar
  10. A Heterogeneous Programmable A/D Converter Array Achieving over 170dB FoMs for 2-500MHz BW and 81.4-58.7dB SNDR
    Zhishuai Zhang, Siyu Huang, Mingyang Gu, Xiyu He, Yunsong Tao, C. Xing, G. Long, Yi Zhong, Nan Sun, Lu Jie
    IEEE Asian Solid-State Circuits Conference (A-SSCC)2025
    DOIIEEE谷歌学术Semantic Scholar
  11. A Hierarchical Compilation Method for Programmable Analog-to-Digital Converter Arrays
    Zhishuai Zhang, Siyu Huang, Yi Zhong, Nan Sun, Lu Jie
    IEEE International Symposium on Circuits and Systems (ISCAS)2025
    DOIIEEE谷歌学术Semantic Scholar
  12. An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buffer Power Gating
    Yunsong Tao, Mingtao Zhan, Mingyang Gu, Xiyu He, Yuxuan He, Zhishuai Zhang, Yi Zhong, Lu Jie, Nan Sun
    IEEE International Solid-State Circuits Conference (ISSCC)2025
    DOIIEEE谷歌学术Semantic Scholar
  13. Live Demonstration: A Programmable A/D Converter Array with Interactive Compiler
    Zhishuai Zhang*, Chitian Yuan*, Jiantao Li, Kun Lin, Yi Zhong, Nan Sun, Lu Jie
    IEEE International Symposium on Circuits and Systems (ISCAS)2025
    DOIIEEE谷歌学术Semantic Scholar
  14. Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency
    Zhishuai Zhang, Mingtao Zhan, Zijie Gao, Siyu Huang, Mingyang Gu, Yunsong Tao, Xiyu He, Chitian Yuan, Yi Zhong, Nan Sun, Lu Jie
    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 10, pp. 5351–53642025
    DOIIEEE谷歌学术Semantic Scholar
  15. Super-saturated complementary carbon nanotube transistors with intrinsic gain singularities
    Guanhua Long, Yuru Wang, Tianshun Bai, Wangchang Li, Panpan Zhang, Xiaosong Deng, Xiang Cai, Meiqi Xi, Yanxia Lin, Xiaohan Cheng, Chenwei Fan, Fan Xia, Xiao Luo, Zhishuai Zhang, Xuelei Liang, Zhiyong Zhang, Nan Sun, Lian-Mao Peng, Youfan Hu
    Nature Communications, vol. 16, 33902025
    DOINature谷歌学术Semantic Scholar
  16. A 1GS/s 6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking
    Zhishuai Zhang, Zijie Gao, Siyu Huang, Nan Sun, Lu Jie
    IEEE Custom Integrated Circuits Conference (CICC)2023
    DOIIEEE谷歌学术Semantic Scholar

著作与专利

著作与教材 4

开源项目

916

Virtuoso-Bridge

604138

面向 Agentic Analog & Mixed-Signal Design 的基础设施

支持本地或远程驱动 Cadence Virtuoso，提供 SKILL 执行、版图、原理图、Maestro 和 Spectre 等工作流，让 LLM Agent 自动调用设计平台，将重复性手工作业转化为自动化工作流。

项目主页 →源代码 →
Cadence VirtuosoSKILLSchematicLayoutMaestroSpectreSSH TunnelCLI-first
Python

ADCToolbox

13238

ADC 建模、频谱与校准工具箱

面向数据转换器分析与验证的开源工具箱。

源代码 →
ADCModelingCalibration
Python

gmoverid-skill

11823

gm/Id 特性仿真与基于 gm/Id 设计的 Agent skill

用于 gm/Id 特性仿真与基于 gm/Id 的模拟设计的 Agent skill。

源代码 →
gm/IdAgent SkillAnalog Design
Python

awesome-ams-skills

284

模拟与混合信号 IC 设计 Agent skills 合集

面向模拟与混合信号（AMS）集成电路设计的 Agent skills 合集。

源代码 →
Awesome ListAMSAgent Skill
HTML

EVAS

63

事件驱动 Verilog-A 仿真器

事件驱动 Verilog-A 仿真器：零依赖、响应快，适合验证时钟、控制与校准逻辑。

源代码 →
Verilog-ASimulatorEvent-driven
Python

奖项与资助

奖项 7

  • ISSCC Jack Kilby Outstanding Student Paper Award
  • IEEE Solid-State Circuits Society 学生电路设计竞赛奖迄今为止唯一的中国籍获奖者
  • ISSCC Student Travel Grant Award
  • 清华大学电子工程系“刘润生优秀助教奖”特等奖
  • 中国教育发展基金会奋进奖学金
  • 志华集成电路奖学金
  • 冯重熙奖学金

资助 2

  • 国家自然科学基金项目主持 1 项
  • 教育部·工信部集成电路高层次人才培养专项奖学金（A 档）
张托肯Token Zhang